The present invention relates to an input circuit, and more particularly, to an input circuit provided with a level shift function operated by an external power supply corresponding to an external interface and an internal power supply corresponding to an internal circuit to shift the voltage of an input circuit from an external device to a voltage adapted to the internal power supply.
Referring to FIG. 1, Japanese Laid-Open Patent Publication No. 2000-183723 describes a first prior art example of an input circuit 150. The input circuit 150 includes a first functional block configured by a first differential amplification circuit 151, a second functional block configured by a level shift circuit 152, and a third functional block configured by a second differential amplification circuit 153.
The first differential amplification circuit 151 and the level shift circuit 152 are connected between a first power supply V1 and a second power supply V2. The second differential amplification circuit 153 is connected between a third power supply V3 and a fourth power supply V4. The second and fourth power supplies V2 and V4 correspond to a ground power supply, the first power supply V1 corresponds to an external power supply, and the third power supply V3 corresponds to an internal power supply at which the potential is lower than that at the external power supply.
The first differential amplification circuit 151 includes resistors 154a and 154b, which are connected in parallel to the first power supply V1, nMOS Trs 155 and 156 having gates for respectively receiving first and second input signals INA and INB, which are external input signals, and a constant current source 157. The first differential amplification circuit 151 amplifies the potential difference of the first and second input signals INA and INB. The first and second input signals INA and INB are signals that complement each other or are differential signals generated so that one of the signals has a median potential relative to the voltage amplitude of the other one of the signals (constant voltage).
The level shift circuit 152 includes an nMOS Tr 158 and a constant current source 159. The level shift circuit 152 shifts the output voltage of the first differential amplification circuit 151 that is provided to the gate of the nMOS Tr 158 to a voltage adapted to the third power supply V3 (internal power supply).
The second differential amplification circuit 153 includes a positive input terminal for receiving the output signal of the level shift circuit 152 and a negative input terminal for receiving a constant voltage signal having a median potential relative to the voltage amplitude of the input signal. The second differential amplification circuit 153 amplifies the potential difference of the two input signals.
FIG. 2 is a waveform diagram of the input circuit 150 in an activated state.
The first power supply V1 is set at 2.5 V, the second power supply V2 is set at 0.0 V, the third power supply V3 is set at 1.2 V, the fourth power supply V4 is set at 0.0 V, and the voltage of the first functional block input signal (in FIG. 2, IN1) serving as an external input signal provided to the first differential amplification circuit 151 is set at 2.2 V/1.8 V.
The first differential amplification circuit 151 amplifies the potential difference of the first functional block input signal IN1 (0.4 V) to generate a second functional block input signal IN2. The voltage of the second functional block input signal IN2 varies within the range of about 0.5 V to 2.5 V in accordance with factors such as the configuration of the first differential amplification circuit 151, the capacity of the devices in the first differential amplification circuit 151, the temperature conditions, and processing conditions.
The level shift circuit 152 shifts the voltage of the second functional block input signal IN2 to a voltage adapted to the third power supply V3 and in the range of 0.0 V to 1.2 V to generate the third functional block input signal IN3.
In this manner, the level shift circuit 152 arranged between the first differential amplification circuit 151 and the second differential amplification circuit 153 prevents a voltage greater than or equal to that of the third power supply V3 (1.2 V) from being applied to the second differential amplification circuit 153. This is because the transistor configuration of the second differential amplification circuit 153 activated by the internal power supply differs from the transistor configuration of the first differential amplification circuit 151 and the level shift circuit 152 activated by the external power supply. For example, the gate oxidized film of the transistor in the second differential amplification circuit 153 is thinner than that of the first differential amplification circuit 151 and the level shift circuit 152. In other words, the withstand voltage of the devices in the second differential amplification circuit 153 is lower than that of the first differential amplification circuit 151 and the level shift circuit 152. Thus, the application of a high voltage exceeding the gate withstand voltage of the transistor (in this case, the first power supply V1) to the second differential amplification circuit 153 damages the devices and causes erroneous operation of the input circuit 150.
Recent progress in manufacturing process technology has miniaturized the transistors of internal circuits. This has lowered the voltages of internal power supplies at a high speed. In contrast, external power supplies rely on external factors, such as external interfaces. Thus, the voltages for the external power supplies have not been lowered as quick as that of the internal power supplies. This has further increased the potential difference between the external power supply and the internal power supply. Therefore, the input circuit must shift the output voltage of the first differential amplification circuit 151 to a voltage that the second differential amplification circuit 153, which is activated by an internal power supply having a lower voltage, is capable of receiving.
The input circuit 150 must not apply a high voltage exceeding the transistor gate withstand voltage to the second differential amplification circuit 153 regardless of whether the input circuit 150 is in an activated state, a standby state, or switched from the activated state to the standby state. In the standby state, the input circuit 150 is disconnected from, for example, the constant current sources 157 and 159 of the input circuit 150 to reduce the current consumption of the input circuit 150.
FIG. 3 is a waveform diagram showing the operation of the input circuit 150 when switching between the activated and standby states. The voltages of the first to fourth power supplies V1 to V4 and the first functional block input signal IN1 (external input signal) are the same as those in FIG. 2.
At time t1, the constant current sources 157 and 159 are disconnected (controlled at current value 0) to switch the input circuit 150 to the standby state. This increases the voltage of the second function block input signal IN2 (output voltage of the first differential amplification circuit 151) to a value close to that of the first power supply V1 (2.5 V). This activates the nMOS Tr 158 of the level shift circuit 152 and increases the voltage of the third function block input signal IN3 (the output voltage of the level shift circuit 152) to a value close to the first power supply V1 (2.5V). Accordingly, the first prior art example has a shortcoming in that a voltage exceeding that of the internal power supply (1.2 V), or the gate withstand voltage, is applied to the second differential amplification circuit 153 when switching from the activated state to the standby state.
To solve this problem, a second prior art example of an input circuit 160 such as that shown in FIG. 4 has been proposed.
The input circuit 160 differs from the first prior art example in the configuration of the first differential amplification circuit. A first differential amplification circuit 161 includes pMOS Trs 162 and 163 having gates for respectively receiving first and second input signals INA and INB, nMOS Trs 164 and 165 that configure a current mirror circuit, and a constant current source 166. The constant current source 166 is connected between a first power supply V1 and the sources of the pMOS Trs 162 and 163.
The first differential amplification circuit 161 amplifies the potential difference of the first and second input signals INA and INB. The first differential amplification circuit 161 is optimal for amplifying an input signal that is close to the ground potential.
FIG. 5 is a waveform diagram showing the operation of the input circuit 160 when switching between the activated and standby states. The voltages of the first to fourth power supplies V1 to V4 are the same as those in FIG. 2, and the voltage of the first functional block input signal IN1 (external input signal) is set at 1.7 V/1.3 V.
At time t1, the constant current sources 166 and 159 are disconnected to switch the input circuit 160 to the standby state. This decreases the voltage of the second function block input signal IN2 (output voltage of the first differential amplification circuit 161) to a value close to that of the second power supply V2 (0.0 V). In response to the voltage decrease, the nMOS Tr 158 of the level shift circuit 152 is inactivated. By decreasing the voltage of the input signal IN2 in this manner, the voltage of the input signal IN3 is prevented from being increased.
However, the gate potential at the nMOS Tr 158 does not decrease to a value less than or equal to a threshold value that immediately inactivates the nMOS Tr 158. The nMOS Tr 158 is inactivated when the output voltage of the first differential amplification circuit 161 (the node voltage between the pMOS Tr 163 and the nMOS Tr 165) is decreased to the ground potential. Thus, the voltage of the third functional block input signal IN3 (the output voltage of the level shift circuit 152) is temporarily increased to a value near that of the first power supply V1 (2.5 V) in a transitional state during period ΔT from when the constant current source 159 is disconnected to when the nMOS Tr 158 is inactivated. As a result, a voltage exceeding that of the third power supply V3 (1.2V) is applied to the second differential amplification circuit 153.
To avoid such temporary voltage increase, for example, the time for disconnecting the constant current source 159 of the second functional block (the current value being decreased to 0) may be changed. For example, timings may be adjusted so that the period ΔT required for inactivating the nMOS Tr 158 in FIG. 5 becomes 0 while intentionally delaying the time at which the current value of the constant current source 159 decreases to 0. This prevents a voltage exceeding the gate withstand voltage from being applied to the second differential amplification circuit 153.
However, the timing adjustment decreases the speed for switching from the activated state to the standby state and also the speed for returning from the standby state again to the activated state. This is not desirable when performing high speed operations. The problems of the first and second prior art examples also occur when the supplied power is negative potential power. An example of such a case will now be discussed.
FIG. 6 is a circuit diagram of a third prior art example of an input circuit 170.
The first to fourth power supplies V11 to V14 are connected to the input circuit 170. The first and third power supplies V11 and V13 are negative potential power supplies, and the second and fourth power supplies V12 and V14 are ground power supplies. The absolute value of the potential at the third power supply V13 is lower than that at the first power supply V11 (|first power supply—second power supply|>|third power supply—fourth power supply|).
The input circuit 170 includes a first differential amplification circuit 171, a level shift circuit 172, and a second differential amplification circuit 173.
The first differential amplification circuit 171 includes resistors 174 and 175, nMOS Trs 176 and 177 having gates for respectively receiving the first and second input signals INA and INB, and a constant current source 178 (nMOS Tr).
The resistor 174 is connected between the second power supply V12 (ground power supply) and the drain of the nMOS Tr 176. The resistor 175 is connected between the second power supply V12 and the nMOS Tr 177. The sources of the nMOS Trs 176 and 177 are connected to the first power supply V11 (negative power supply) via the constant current source 178. The gate of the nMOS Tr configuring the constant current source 178 is provided with a current control signal S1 that controls the activation and inactivation of the transistor.
The level shift circuit 172 includes a pMOS Tr 179 and a constant current source 180 (pMOS Tr). The output voltage of the first differential amplification circuit 171 is applied to the gate of the pMOS Tr 179. The gate of the pMOS Tr configuring the constant current source 180 is provided with a current control signal /S1 (the signals S1 and /S1 are signals that complement each other) that controls the activation and inactivation of the pMOS Tr.
FIG. 7 is a waveform diagram showing the operation of the input circuit 170 when switching between the activated and standby states. The voltages are set so that, for example, the first power supply V11 is −3.3 V, the second power supply V12 is 0.0 V, the third power supply V13 is −1.2 V, the fourth power supply V14 is 0.0 V, and the external input signal (the first functional block input signal IN1 in FIG. 7) is −2.0 V /−2.4 V.
At time t1, the current control signal S1 is low (the current control signal /S1 being high). This disconnects the constant current sources 178 and 180. When the input circuit 170 enters the standby state, the voltage of the second functional block input signal IN2 (the output voltage of the first differential amplification circuit 171) is increased to a value that is close to that of the second power supply V12 (ground potential 0.0 V). This inactivates the pMOS Tr 179 of the level shift circuit 172.
However, the voltage of the third functional block input signal IN3 (the output voltage of the level shift circuit 172) is temporarily decreased to a value near that of the first power supply V11 (−3.3 V) in a transitional state during period ΔT from when the constant current source 180 is disconnected to when the pMOS Tr 179 is inactivated. As a result, a high voltage (in this case, absolute value) exceeding that of the third power supply V13 (−1.2V) is applied to the second differential amplification circuit 173. To avoid such temporary voltage increase, timings may be adjusted so that the period ΔT required for inactivating the pMOS Tr 179 in FIG. 7 becomes 0 while intentionally delaying the time at which the pMOS Tr configuring the constant current source 180 is inactivated. This would not satisfy the afore-mentioned demand for increasing the speed of the input circuit.